Digital Electronics Test
9's complement of 56 is _____.
A 1 us pulse can be converted into a 1 ms pulse by using a _____ multivibrator(MVR).
A 4-bit synchronous counter uses flip-flops with the propagation delay time of 25nsec each. The maximum possible time required for the change of state will be _____.
A circuit has an output that is determined by the present input as well as the previous output states. The circuit is known as _____.
A flip-flop may be built with
A half adder consists of an _____ gate and a _____ gate.
A J-K F/F may be obtained by adding__________ .
A memory device that contains a SRAM and EEPROM in the same chip is called _____.
A memory in which the contents get erased when power-failure occurs is called_______ .
A monostable circuit gives a pulse-width output having tp=0.3 Rx.Cx. The device employed is likely to be_____ .
A monostable circuit uses a timing register of 10k ohms and a capacitor of 0.1µF capacity respectively. Its pulse-width will be approximately_____ .
A multiplexer having 32 data input lines needs _____ select lines.
A multiplexer tree is needed when the number of inputs is more than _____.
A PLA consists of
A semi-conductor ROM is basically a ________.
A transparent latch consists of a__________ .
A triggerable one-shot monostable MVR _____.
A twisted ring counter consisting of 6 F/F will have
A universal register _____.
Adding inverters to the input of an OR gate produces the _____ logic function.
Decimal counters using flip flops and feedback are more popular than a decimal counter of ring counter type because of _____.
For a 12-bit ADC, the range of input-voltage is (0 to +10v).The voltage corresponding to LSB is _____.
For a flip-flop with provisions of preset and clear__________.
Hexadecimal equivalent of (268)10 is_______ .
How many memory locations can 14 address bits access?
If an ADC with 8-bit output gives full-scale deflection for 12v analog-signal, its resolution is _____.
If in a clocked R-S F/F, point R is joined to point S through an inverter, the circuit will become a___________ .
If in a clocked R-S Flip Flop, point R is joined to point S through an inverter, the circuit will become a___________ .
If inverters are added to the inputs of AND gate, the logic function is _____.
In a 4-bit weighted-register DAC, the resistor value corresponding to MSB is 2k ohm. The resistor value corresponding to LSB will be _____.
In a karnaugh map, a quad eliminates _____ variables.
In a microprocessor, the adder circuit is a part of
In a shift register, complemented output point Ā of the last flip-flop is joined to point J of the first flip-flop while its point K is joined to point A of the last flip-flop. The circuit will wor...
In an IC-555-timer, the load can be connected _____.
In an XNOR gate, input A is high and B is low. The output will _____.
In BCD to 7 segment decoder/driver, the input is 1000. The segments which will be lit are _____.
In sequential circuits, memory elements are _____.
In the BCD number system, subtraction is done by the______ method.
In the floating point system, the exponent is written in __________ notation.
LSI and VLSI devices use the _____ technology.
One of the two states of a circuit is stable and the others are quasi-stable. The circuit is a _____ circuit.
One OR gate can work as a _____ comparator.
Pocket calculators use the_________ system.
Race condition occurs in _____.
Semi-conductor memories are widely used because of their__________ .
Shift-registers most commonly use _____.
Shifting the contents of a shift register one place to the left is equivalent to
The addition of hexadecimal number DF16 + AC16
The address bus width of a memory of size (1024*8) bit is _____.
The boolean expression xy + xz +xyz ( xy + z ) is equal to _____.
The boolean expression XY+X+XY is equal to _____.
The comparison time of ADC-0800 is in the range of _____.
The counting sequence of a uniform counter is 000,001,011,111,110,100.The counter is a _____.
The design of a sequential circuit requires the use of _____.
The minimum number of resistors required in a 4-bit network of weighted resistor type DAC is ______.
The most important advantage of CMOS is its _____.
The most suitable gate for comparing two bits is the _____ gate.
The number of 4-line-to-16-line decoders required to make an 8-line-to-250-line decoder is_____ .
The outputs Q and ¯Q of a master-slave S-R F/F are connected to its S and R inputs respectively. Its output Q, when clock pulses are applied, will be__________.
The race-around condition occurs in J-K F/F when____________ .
The time taken by an ADC to perform a conversion is usually referred to as
The write-cycle time of a memory is 200 nsec. The maximum rate at which data can be stored is________ .
Triggering action can be obtained in a J-K F/F by __________ .
Two mod-3 counters are cascaded. The circuit will behave as a _____.
What would be the value of X if (110001)2= X10?
When a large number of analog-signals are to be converted to the digital form, the most suitable ADC is _________ converter.
Which family has the fastest speed?
Which of the following memories uses an index-hole to provide timing signals?
While designing a counter circuit, the preferred type of flip-flop is _____.