VLSI Test
A fast CMOS circuit requires that the gm___________. (Where gm means transconductance).
A signal data object in VHDL is an object with_______________.
An active current mirror means that ___________.
Contacts between the metal layers are known as _____________.
Floating point data types provide an approximation of ___________.
For a given total bias current, the gain of a differential pair is________ more than the CS Stage.
For an npn Bipolar Transistor, gm ___________.
For the Orbit Process, the n-active and p-active regions have_________.
High Electron Mobility Transistors(HEMT) are formed using alternating layers of _______________.
How many Pass transistors can be connected in a series?
If length (L) and width (W) are both scaled down by α, the area is scaled ___________. ron
If length (L) and width (W) are both scaled down by α, the area is scaled ___________. (Power Speed Product PT)
If length (L) and width (W) are both scaled down by α, the area is scaled down by __________.
In comparison with SSI ,VLSI has ____________ components per chip.
In general, VDD and VSS are always distributed upon ____________.
In the BiCMOS process, the basic inverter is made by __________.
In the Cascode structure, the maximum voltage gain is roughly equal to ____________.
In the Folded Cascode structure, ____________.
In VHDL, the prefix "V" stands for ___________________.
In VHDL,the order of the concurrent statements must be_________.
In which condition is the Case statement used?
In which region should MOS be operated as an amplifier?
Latch up introduces_________.
LSI and VLSI devices use_____________ technology.
MOS current sources are used to generate __________.
MOS in the Common Gate Configuration provides___________.
Photolithography in IC Fabrication is___________.
QHDL(Hardware Description Language) is used for _____________.
Stick diagrams are used to __________.
The Cascode structure ___________.
The CMRR (common-mode rejection ratio) of a differential amplifier must be ___________.
The Double Metal MOS process is used to ____________.
The gain of the CG configuration is __________ the CS configuration.
The most commonly used model for scaling is ___________ .
The separation between the Thinox Regions is of __________ .
The two metal layers are laid in a way that ______________.
Under what condition does the Frenkel defect take place?
Wafers with a____________ are needed for the fabrication of VLSI.
We need only __________ to make a 2:1 MUX with a pass transistor logic.
What does Fick's law deal with?
What does the Programmable Logic Array(PLA) consist of?
What exactly is Behavioral Modeling in VHDL?
What function does the scalar data type perform in VHDL?
What is Generic Array Logic(GAL) based on?
What is Metallization in IC Fabrication?
What is the body effect on the input impedance of the Common Gate Configuration?
What is the function of the Alias statement?
When do Sequential statements appear in a program?
When is the Boundary Scan Test (BST) used?
Which among the following conditions qualifies for a Latch-up in CMOS circuit condition?
Which diode is present in the GaAs MESFET circuit?
Which execution platform is used for a behaviour-level VHDL?
Which IEEE standard is used by VHDL 93 ?
Which kind of problem is eliminated by the NMOS superbuffers?
Which kind of signal is converted into in the common source arrangement of the transistor?
Which of the following can act as a dopant for the formation of N-type gallium arsenide material?
Which of the following is the fastest technology in terms of propagation delay?
Which of the following parameters is advantageous in the case of BiCMOS technology?
Which of the following statements does not perform any action?
Which one of the following has the lowest power dissipation?
Which one of the following is a concurrent statement?
Which one of the following is not a CMOS fabrication technique?
Which one of the following is not a mode for ports in VHDL?
Which one of the following is not a sequential statement in VHDL?
Which one of the following is not true about packages in VHDL?
Which one of the following is true about the fabrication of capacitors in the ICs?
Which one of the following stages is used in the Cascode configuration?
Which one of the following statements is not correct about an entity in VHDL?
Why is the fabrication of inductors in ICs not practical?